VLSI PROJECT TITLES
* A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction
* A Current-Starved Inverter-based Differential Amplifier Design for Ultra-Low Power Applications
* A Fast Low-Light Multi-Image Fusion with Online Image Restoration
* A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS
* A Low Power Fault Tolerant Reversible Decoder using MOS Transistor
* A Low Power Single Phase Clock Distribution using VLSI technology
* A Novel modulo Adder for 2n-2k-1 Residue Number System
* A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier
* A Topology-Based Model for Railway Train Control Systems
* Achieving Reduced Area By Multi-Bit Flip Flop Design
* An Analysis of SOBEL and GABOR Image Filters for Identifying Fish
* An Efficient Denoising Architecture for Removal of Impulse Noise in Images
* An Efficient High Speed Wallace Tree Multiplier
* An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic
* An Interactive RFID-based Bracelet for Airport Luggage Tracking System
* Area-Delay Efficient Binary Adders in QCA
* Asynchronous Design of Energy Efficient Full Adder
* Background Subtraction Based on Threshold detection using Modified K-Means Algorithm
* Comparison of Static and Dynamic Printed Organic Shift Registers
* CORDIC based Fast Radix-2 DCT Algorithm
* Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
* Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
* Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD Tool
* Design of High Speed Low Power Viterbi Decoder for TCM System
* Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT
* Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop
* FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix-2by4 Algorithms
* Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max Approximation Error
* FPGA Implementation of Pipelined Architecture For SPIHT Algorithm
* Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
* Hardware Implementation of a Digital Watermarking System for Video Authentication
* High-Throughput Compact Delay-Insensitive Asynchronous NOC Router
* High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic
* Improvement of the Security of Zigbee by a New Chaotic Algorithm
* Least Significant Bit Matching Steganalysis based on Feature Analysis
* Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing
* Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials
* Low-Complexity Multiplier for GF (2m) based on All-One Polynomials
* Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Soft-core Processor
* Low-Power Digital Signal Processing Using Approximate Adders
* * Low-Power, High-Throughput and Low-Area Adaptive FIR Filter based on Distributed Arithmetic
* Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT
* Modified Gradient Search for Level Set Based Image Segmentation
* Multicarrier Systems based on Multistage Layered IFFT Structure
* Optical Flow Estimation for Flame Detection in Videos
* Parallel AES Encryption Engines for Many-Core Processor Arrays
* Performance Analysis of a New CMOS Output Buffer
* Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
* Pipelined Radix-2k Feed forward FFT Architectures
* Prototype of a Fingerprint Based Licensing System For Driving
* Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS
* Reconfigurable Processor for Binary Image Processing
* Reduced-Complexity LCC Reed–Solomon Decoder based on Unified Syndrome Computation
* Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
* Reverse Circle Cipher for Personal and Network Security
* RFID-based Location System for Forest Search and Rescue Missions
* RFID-based Tracking System Preventing Trees Extinction and Deforestation
* Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter
* Secure Transmission in Downlink Cellular Network with a Cooperative Jammer
* Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation
* Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes
* Shadow Removal for Background Subtraction Using Illumination Invariant Measures
* Teaching HW/SW Co-Design with a Public Key Cryptography Application
* Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
* The Security Technology and Tendency of New Energy Vehicle in Future
VLSI & FPGA IEEE 2013 PROJECT TITLES
* A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction
* A Current-Starved Inverter-based Differential Amplifier Design for Ultra-Low Power Applications
* A Fast Low-Light Multi-Image Fusion with Online Image Restoration
* A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS
* A Low Power Fault Tolerant Reversible Decoder using MOS Transistor
* A Low Power Single Phase Clock Distribution using VLSI technology
* A Novel modulo Adder for 2n-2k-1 Residue Number System
* A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier
* A Topology-Based Model for Railway Train Control Systems
* Achieving Reduced Area By Multi-Bit Flip Flop Design
* An Analysis of SOBEL and GABOR Image Filters for Identifying Fish
* An Efficient Denoising Architecture for Removal of Impulse Noise in Images
* An Efficient High Speed Wallace Tree Multiplier
* An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic
* An Interactive RFID-based Bracelet for Airport Luggage Tracking System
* Area-Delay Efficient Binary Adders in QCA
* Asynchronous Design of Energy Efficient Full Adder
* Background Subtraction Based on Threshold detection using Modified K-Means Algorithm
* Comparison of Static and Dynamic Printed Organic Shift Registers
* CORDIC based Fast Radix-2 DCT Algorithm
* Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
* Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
* Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD Tool
* Design of High Speed Low Power Viterbi Decoder for TCM System
* Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT
* Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop
* FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix-2by4 Algorithms
* Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max Approximation Error
* FPGA Implementation of Pipelined Architecture For SPIHT Algorithm
* Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
* Hardware Implementation of a Digital Watermarking System for Video Authentication
* High-Throughput Compact Delay-Insensitive Asynchronous NOC Router
* High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic
* Improvement of the Security of Zigbee by a New Chaotic Algorithm
* Least Significant Bit Matching Steganalysis based on Feature Analysis
* Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing
* Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials
* Low-Complexity Multiplier for GF (2m) based on All-One Polynomials
* Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Soft-core Processor
* Low-Power Digital Signal Processing Using Approximate Adders
* * Low-Power, High-Throughput and Low-Area Adaptive FIR Filter based on Distributed Arithmetic
* Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT
* Modified Gradient Search for Level Set Based Image Segmentation
* Multicarrier Systems based on Multistage Layered IFFT Structure
* Optical Flow Estimation for Flame Detection in Videos
* Parallel AES Encryption Engines for Many-Core Processor Arrays
* Performance Analysis of a New CMOS Output Buffer
* Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
* Pipelined Radix-2k Feed forward FFT Architectures
* Prototype of a Fingerprint Based Licensing System For Driving
* Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS
* Reconfigurable Processor for Binary Image Processing
* Reduced-Complexity LCC Reed–Solomon Decoder based on Unified Syndrome Computation
* Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
* Reverse Circle Cipher for Personal and Network Security
* RFID-based Location System for Forest Search and Rescue Missions
* RFID-based Tracking System Preventing Trees Extinction and Deforestation
* Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter
* Secure Transmission in Downlink Cellular Network with a Cooperative Jammer
* Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation
* Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes
* Shadow Removal for Background Subtraction Using Illumination Invariant Measures
* Teaching HW/SW Co-Design with a Public Key Cryptography Application
* Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
* The Security Technology and Tendency of New Energy Vehicle in Future
FOR MORE TITLES VISIT OUR OFFICE DIRECTLY
VISIT OUR WEBSITE / BLOGS FOR DOWNLOADS, TITLES & ABSTRACTS
YOUR OWN IDEAS CAN ALSO BE IMPLEMENTED
All Projects will come with
“VLSI HARDWARE KIT”
Why NCCT
Complete Guidance * On time Completion * Excellent Support * Multi platform Training * Flexibility
PROJECTS SUPPORTS & DELIVERABLES
· Project Abstracts · IEEE Paper, Project IEEE Base / Reference Paper
· Project Block Diagram
· Project Circuit Diagram
· PPT & Review preparation for Viva
· Project Report Guidance
· Project Demo & Explanation
· Working Procedure & Screen Shots
· Datasheets, Manuals & Reference Books in DVD
· Project Kit, * “VLSI Hardware Kit” *
· Project Acceptance / Completion Certificate
VLSI PROJECTS USING
--------------------------------------* VLSI Projects using Spartan3 FPGA Kit (Spartan3AN FPGA Kit / Xilinx ISE / Xilinx EDK)
* Embedded Projects using VLSI FPGA Spartan Processors (Spartan3 FPGA Kit / Xilinx ISE / Xilinx EDK)
VLSI PROJECT DOMAINS
----------------------------------------COMMUNICATION SYSTEMS, ARCHITECTURAL DESIGN, PROTOCOL DESIGN, LOW POWER DESIGN, IMAGE PROCESSING, STEGANOGRAPHY, SURVEILLANCE SYSTEMS, CRYPTOGRAPHY, SOFTCORE PROCESSOR DESIGN, REAL TIME AUDIO / VIDEO PROCESSING, SECURITY PROTOCOLS, POWER ANALYZER
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